1. Field of the Invention
This invention generally relates to the field of integrated circuit testing, and in particular to systems and methods for self-testing an integrated circuit.
2. Description of the Related Art
An integrated circuit (also known as an “IC”, “microchip”, “silicon chip”, “computer chip,” or “chip”) is a miniaturized electronic circuit that has been manufactured on a semiconductor substrate composed of, for example, silicon, gallium arsenide (“GaAs”), or other types of semiconductor materials. An IC is typically packaged in a hermetically sealed case or a non-hermetic plastic capsule, with leads extending from it for input, output, and power-supply connections, and for other connections that may be necessary when the IC is put to use.
The two main advantages of ICs over discrete circuits are cost and performance. The cost is low because ICs, with all their components, are typically printed as a unit by photolithography and not constructed a transistor at a time. At present, IC areas range from a few square millimeters (mm2) to around 250 mm2, with up to approximately one million transistors per square millimeter.
Generally, while the cost of designing and developing a complex IC may be high, when this cost is spread across typically millions of production units the individual IC cost is minimized significantly. Additionally, the performance of ICs is high because the small size allows short traces which in turn allows low power logic (such as CMOS) to be utilized at fast switching speeds.
ICs have consistently migrated to smaller feature sizes over the years, allowing more circuitry to be packed on each chip. As the feature size shrinks, almost everything improves because the cost and the power consumption go down and the speed of the IC goes up. Since these gains are apparent to the end user, there is fierce competition among the manufacturers to use finer geometries and thinner line widths in producing newer ICs.
Manufacturers also fiercely compete to produce reliable IC designs because their respective reputations depend upon the reliability of their ICs. As the line width within an integrated circuit chip continues to shrink, this reliability becomes more difficult to achieve. Therefore, an ongoing challenge for the IC manufacturers is to increase the number and density of transistors on an IC without sacrificing reliability or suffering decreasing chip yields due to malfunctioning parts.
In addition to the problems associated with shrinking feature sizes in ICs, another approach to increasing the complexity of an IC includes the System-on-a-Chip (“SOC”) approach, which also raises testing problems. In this approach, components traditionally manufactured as separate ICs, to be wired together on a printed circuit board, are designed to occupy a single IC that contains memory, microprocessor(s), peripheral interfaces, Input/Output logic control, data converters, and other components, together defining the whole electronic system.
Unfortunately, this increased complexity comes at a cost because while these process technologies allow placing tens of millions of gates onto an IC, they create serious test problems as to test development time and test application time for testing the IC for process defects. One standard way for testing ICs involves using an external memory tester (such as, for example, an Automatic Test Equipment “ATE”) at the manufacturing site. As an example, FIG. 1 shows a block diagram of an example of an implementation of a known IC test system 100 that may include an IC under test 102 in signal communication with an external memory tester 104 via signal paths 106. The signal paths 106 may be wires that are electrically connected to leads 108 of the IC under test 102. It is appreciated by those skilled in the art that as the complexity of the IC under test 102 increases it becomes more difficult to properly test the IC under test 102 with the external memory tester 104.
In operation, the external memory tester 104 supplies power and applies test patterns to the IC to detect faults. Unfortunately, external memory testers may only test a limited number of ICs at a time, and the test speed is typically limited by the external bus speed. Consequently, these approaches for testing are expensive in terms of time requirements and equipment costs.
Attempts to solve this problem includes design for test (“DFT”) approaches such as, for example, scan-test design, Logic built-in self-test (“BIST” or “Logic BIST”), and other similar technologies. DFT is an approach for IC and printed circuit board manufacturers to realize significant economic savings. At the device level, it sometimes replaces the traditional functional testing role in which ICs are tested at their I/O for functional performance as shown in FIG. 1.
As a result, BIST units are now commonly incorporated into ICs and ATE is presently simplified to the extent that the only necessary functions are to supply power (and sometimes a clock signal) to the IC, and to monitor a single output signal from the chip. The on-chip BIST unit generates all the test patterns and asserts (or de-asserts) the output signal if the chip passes the functionality test. The BIST may be configured to run every time the chip is powered-on, or the BIST may be configured to run only when a test mode signal is asserted.
As an example, FIG. 2 shows a block diagram of an example of an implementation of a known DFT approach in a DFT enabled IC 200. The DFT enabled IC 200 may include an IC core 202, BIST logic 204, and a test module 206. The test module may be in signal communication with the BIST logic 204 via a signal path 208, which may be a test bus. The IC core 202 may be in signal communication with the BIST logic 204 via a plurality of signal paths 210. The IC core 202 is the die (i.e., the IC circuitry) designed into the IC and may include combinational logic (not shown) that is capable of receiving a capture test pattern of data from the test module 206. Examples of the IC circuitry may include a processor, controller, application specific integrated circuit (“ASIC”), digital signal processor, memory module, RF chip-set, SOC, or other types of devices. The BIST logic 204 may include a loading circuit (not shown) for loading a shift pattern from the test module 206.
In an example of operation, the test module 206 may be logic circuitry that is programmable for running a plurality of tests on the IC core 202 in order to detect any potential faults of the IC core 202. As such, the BIST logic 204 may operate according to some predetermined algorithm, controlled by the test module 206, to verify the functionality of the internal IC core 202.
In FIG. 3, a block diagram of an example of an implementation of a known DFT approach for the BIST logic of a DFT enabled IC 300 is shown. The DFT enabled IC 300 may include combinational logic 302 and a loading circuit 304. The combinational logic 304 is part of an IC core (not shown) of the DFT enabled IC 300 and the loading circuit 302 is part of the BIST logic of a DFT enabled IC 300. For simplicity, only three sequential elements 306, 308, and 310 are shown, but it is appreciated by those skilled in the art that the loading circuit 304 may include a plurality of sequential elements where the number of sequential elements is determined by the design of the combinational logic and testing algorithms. The sequential elements 306, 308, and 310 may be implemented as D-latch flip-flops having data (“D”), scan-in (“Si”) and scan-enable (“Se”) inputs, sequential output (“Q”), and a clock input (“CLK”). The combinational logic 302 may be in signal communication with first sequential element 306 via signal paths 312 and 314, the second sequential element 308 via signal paths 316 and 318, and the third sequential element 310 via signal paths 320 and 322.
In an example of operation, the loading circuit 304 receives a shift test pattern of data 324 via the scan-in input of the first sequential element 306 and the combinational logic 302 receives a capture test pattern of data 326. The loading circuit 304 shifts the shift test pattern of data 324 through the loading circuit 304 utilizing a scan enable signal 328 and clock signal 330. The loading circuit 304 then passes the loaded shift test pattern of data 324 to the combinational logic 302 via signal paths 314, 318, and 322, and, in response, receives a resulting logic test pattern of data from the combinational logic 302 via signal paths 312, 316, and 320.
Unfortunately, this approach consumes significant power and time because in the shift mode of operation the loading circuit is passing signals to the combinational logic 302 via signal paths 314, 318, and 322, which is resulting in the combinational logic 302 receiving the signals, processing them, and producing resulting signals that are sent to the loading circuit 304. Additionally, because the combinational logic 302 is operating on the unloaded signal produced by the loading circuit 304 while it is shifting, the combinational logic 302 will require time to settle before the loading circuit 304 may pass the fully loaded shift test pattern of data.
Therefore, there is a need for a system and method capable of testing complex ICs quickly and at low-power.